STM32N6 NPU Deployment — Politecnico di Milano  1.0
Documentation for Neural Network Deployment on STM32N6 NPU - Politecnico di Milano 2024-2025
Part 1 — Narrative Explanations

Part 1
Narrative Explanations — Six Chapters

These chapters build the complete conceptual foundation for the project — from the basics of edge computing to a detailed analysis of our results. No prior knowledge is assumed.

Chapter 1 — Introduction
Edge Computing • Embedded Systems • AI • Quantization
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Chapter 2 — Hardware
STM32N6570-DK • Neural-ART NPU • Memory Architecture • DCMIPP
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Chapter 3 — Toolchain
Model Zoo • ModelZoo Services • ST Edge AI Core • STM32CubeIDE
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Chapter 4 — Deployment Workflow
Model Selection • Quantization • Profiling • Flash • Validation
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Chapter 5 — Case Studies
MoveNet Lightning • YOLOv8n-pose • TinyBERT
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Chapter 6 — Results & Analysis
NPU Offload Comparison • Latency Analysis • Conclusions
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