main.c

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#include "cmw_camera.h"
#include "stm32n6570_discovery_bus.h"
#include "stm32n6570_discovery_lcd.h"
#include "stm32n6570_discovery_xspi.h"
#include "stm32n6570_discovery.h"
#include "stm32_lcd.h"
#include "app_fuseprogramming.h"
#include "stm32_lcd_ex.h"
#include "app_postprocess.h"
#include "ll_aton_runtime.h"     
#include "app_camerapipeline.h"
#include "main.h"
#include <stdio.h>
#include "app_config.h"          
#include "crop_img.h"
#include "stlogo.h"
#include "utils.h"
 
#if POSTPROCESS_TYPE == POSTPROCESS_MPE_YOLO_V8_UF
  #include "display_mpe.h"   
#elif POSTPROCESS_TYPE == POSTPROCESS_SPE_MOVENET_UF
  #include "display_spe.h"   
#else
  #error "PostProcessing type not supported"
#endif
 
#define MAX_NUMBER_OUTPUT 5
 
#define LCD_FG_WIDTH  SCREEN_WIDTH
 
#define LCD_FG_HEIGHT SCREEN_HEIGHT
 
#define LCD_FG_FRAMEBUFFER_SIZE  (LCD_FG_WIDTH * LCD_FG_HEIGHT * 2)
 
typedef struct
{
  uint32_t X0;     
  uint32_t Y0;     
  uint32_t XSize;  
  uint32_t YSize;  
} Rectangle_TypeDef;
 
Rectangle_TypeDef lcd_bg_area = {
#if ASPECT_RATIO_MODE == ASPECT_RATIO_CROP || ASPECT_RATIO_MODE == ASPECT_RATIO_FIT
  .X0 = (LCD_FG_WIDTH - LCD_FG_HEIGHT) / 2,   
#else
  .X0 = 0,
#endif
  .Y0 = 0,
  .XSize = 0,   
  .YSize = 0,   
};
 
Rectangle_TypeDef lcd_fg_area = {
  .X0 = 0,
  .Y0 = 0,
  .XSize = LCD_FG_WIDTH,
  .YSize = LCD_FG_HEIGHT,
};
 
#if POSTPROCESS_TYPE == POSTPROCESS_MPE_YOLO_V8_UF
  mpe_yolov8_pp_static_param_t pp_params;  
  mpe_pp_out_t pp_output;                  
#elif POSTPROCESS_TYPE == POSTPROCESS_SPE_MOVENET_UF
  spe_movenet_pp_static_param_t pp_params; 
  spe_pp_out_t pp_output;                  
#endif
 
volatile int32_t cameraFrameReceived;
 
uint8_t *nn_in;
 
BSP_LCD_LayerConfig_t LayerConfig = {0};
 
#define ALIGN_TO_16(value) (((value) + 15) & ~15)
 
#if (NN_WIDTH * NN_BPP) != ALIGN_TO_16(NN_WIDTH * NN_BPP)
#define DCMIPP_OUT_NN_LEN (ALIGN_TO_16(NN_WIDTH * NN_BPP) * NN_HEIGHT)
#define DCMIPP_OUT_NN_BUFF_LEN (DCMIPP_OUT_NN_LEN + 32 - DCMIPP_OUT_NN_LEN%32)
__attribute__ ((aligned (32)))
uint8_t dcmipp_out_nn[DCMIPP_OUT_NN_BUFF_LEN];
#else
uint8_t *dcmipp_out_nn;
#endif
 
__attribute__ ((section (".psram_bss")))
__attribute__ ((aligned (32)))
uint8_t lcd_bg_buffer[800 * 480 * 2];
 
__attribute__ ((section (".psram_bss")))
__attribute__ ((aligned (32)))
uint8_t lcd_fg_buffer[2][LCD_FG_WIDTH * LCD_FG_HEIGHT * 2];
 
static int lcd_fg_buffer_rd_idx;
 
/* Forward declarations */
static void SystemClock_Config(void);
static void NPURam_enable(void);
static void NPUCache_config(void);
static void Display_NetworkOutput(void *p_postprocess, uint32_t inference_ms);
static void LCD_init(void);
static void Security_Config(void);
static void set_clk_sleep_mode(void);
static void IAC_Config(void);
static void Display_WelcomeScreen(void);
static void Hardware_init(void);
static void NeuralNetwork_init(uint32_t *nnin_length, float32_t *nn_out[],
                                int *number_output, int32_t nn_out_len[]);
 
 
int main(void)
{
  Hardware_init();
 
  /*** NN Init ****************************************************************/
  uint32_t pitch_nn = 0;
  uint32_t nn_in_len = 0;
  int number_output = 0;
  float32_t *nn_out[MAX_NUMBER_OUTPUT] = {0};
  int32_t nn_out_len[MAX_NUMBER_OUTPUT] = {0};
 
  LL_ATON_DECLARE_NAMED_NN_INSTANCE_AND_INTERFACE(Default);
  NeuralNetwork_init(&nn_in_len, nn_out, &number_output, nn_out_len);
 
  /*** Post Processing Init ***************************************************/
  app_postprocess_init(&pp_params);
 
  /*** Camera Init ************************************************************/
  CameraPipeline_Init(&lcd_bg_area.XSize, &lcd_bg_area.YSize, &pitch_nn);
 
  LCD_init();
 
  CameraPipeline_DisplayPipe_Start(lcd_bg_buffer, CMW_MODE_CONTINUOUS);
 
  /*** App Loop ***************************************************************/
  while (1)
  {
    CameraPipeline_IspUpdate();
 
    if (pitch_nn != (NN_WIDTH * NN_BPP))
    {
      CameraPipeline_NNPipe_Start(dcmipp_out_nn, CMW_MODE_SNAPSHOT);
    }
    else
    {
      CameraPipeline_NNPipe_Start(nn_in, CMW_MODE_SNAPSHOT);
    }
 
    while (cameraFrameReceived == 0) {};
    cameraFrameReceived = 0;
 
    uint32_t ts[2] = { 0 };
 
    if (pitch_nn != (NN_WIDTH * NN_BPP))
    {
      SCB_InvalidateDCache_by_Addr(dcmipp_out_nn, sizeof(dcmipp_out_nn));
      img_crop(dcmipp_out_nn, nn_in, pitch_nn, NN_WIDTH, NN_HEIGHT, NN_BPP);
      SCB_CleanInvalidateDCache_by_Addr(nn_in, nn_in_len);
    }
 
    ts[0] = HAL_GetTick();
 
    LL_ATON_RT_Main(&NN_Instance_Default);
 
    ts[1] = HAL_GetTick();
 
    int32_t ret = app_postprocess_run((void **) nn_out, number_output,
                                       &pp_output, &pp_params);
    assert(ret == 0);
 
    Display_NetworkOutput(&pp_output, ts[1] - ts[0]);
 
    for (int i = 0; i < number_output; i++)
    {
      float32_t *tmp = nn_out[i];
      SCB_InvalidateDCache_by_Addr(tmp, nn_out_len[i]);
    }
  }
}
 
 
static void Hardware_init(void)
{
  /* Enable Instruction Cache for faster code execution */
  MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_ICACTIVE_Msk;
 
  /* Reset CPU clock to HSI before reconfiguring PLLs */
  __HAL_RCC_CPUCLK_CONFIG(RCC_CPUCLKSOURCE_HSI);
  __HAL_RCC_SYSCLK_CONFIG(RCC_SYSCLKSOURCE_HSI);
 
  HAL_Init();
 
  SCB_EnableICache();
 
#if defined(USE_DCACHE)
  /* Enable Data Cache (controlled by USE_DCACHE in app_config.h) */
  MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_DCACTIVE_Msk;
  SCB_EnableDCache();
#endif
 
  SystemClock_Config();   /* Configure PLLs: CPU@800MHz, NPU@1000MHz */
  NPURam_enable();        /* Enable all 4 NPU SRAM banks */
  Fuse_Programming();     /* Program OTP fuses if needed */
  NPUCache_config();      /* Initialize NPU AXI cache */
 
  /* Initialize external OctoFlash (128MB) — stores model weights */
  BSP_XSPI_RAM_Init(0);
  BSP_XSPI_RAM_EnableMemoryMappedMode(0);
 
  BSP_XSPI_NOR_Init_t NOR_Init;
  NOR_Init.InterfaceMode = BSP_XSPI_NOR_OPI_MODE;
  NOR_Init.TransferRate = BSP_XSPI_NOR_DTR_TRANSFER;
  BSP_XSPI_NOR_Init(0, &NOR_Init);
  BSP_XSPI_NOR_EnableMemoryMappedMode(0);
 
  Security_Config();  /* Grant secure access to NPU, DCMIPP, LTDC, DMA2D */
  IAC_Config();       /* Configure Illegal Access Controller */
  set_clk_sleep_mode(); /* Keep NPU + display clocks active during sleep */
}
 
 
static void NeuralNetwork_init(uint32_t *nnin_length, float32_t *nn_out[],
                                int *number_output, int32_t nn_out_len[])
{
  const LL_Buffer_InfoTypeDef *nn_in_info = LL_ATON_Input_Buffers_Info_Default();
  const LL_Buffer_InfoTypeDef *nn_out_info = LL_ATON_Output_Buffers_Info_Default();
 
  nn_in = (uint8_t *) LL_Buffer_addr_start(&nn_in_info[0]);
 
  while (nn_out_info[*number_output].name != NULL)
  {
    (*number_output)++;
  }
  assert(*number_output <= MAX_NUMBER_OUTPUT);
 
  for (int i = 0; i < *number_output; i++)
  {
    nn_out[i] = (float32_t *) LL_Buffer_addr_start(&nn_out_info[i]);
    nn_out_len[i] = LL_Buffer_len(&nn_out_info[i]);
  }
 
  *nnin_length = LL_Buffer_len(&nn_in_info[0]);
}
 
 
static void NPURam_enable(void)
{
  __HAL_RCC_NPU_CLK_ENABLE();
  __HAL_RCC_NPU_FORCE_RESET();
  __HAL_RCC_NPU_RELEASE_RESET();
 
  __HAL_RCC_AXISRAM3_MEM_CLK_ENABLE();
  __HAL_RCC_AXISRAM4_MEM_CLK_ENABLE();
  __HAL_RCC_AXISRAM5_MEM_CLK_ENABLE();
  __HAL_RCC_AXISRAM6_MEM_CLK_ENABLE();
  __HAL_RCC_RAMCFG_CLK_ENABLE();
 
  RAMCFG_HandleTypeDef hramcfg = {0};
  hramcfg.Instance = RAMCFG_SRAM3_AXI; HAL_RAMCFG_EnableAXISRAM(&hramcfg);
  hramcfg.Instance = RAMCFG_SRAM4_AXI; HAL_RAMCFG_EnableAXISRAM(&hramcfg);
  hramcfg.Instance = RAMCFG_SRAM5_AXI; HAL_RAMCFG_EnableAXISRAM(&hramcfg);
  hramcfg.Instance = RAMCFG_SRAM6_AXI; HAL_RAMCFG_EnableAXISRAM(&hramcfg);
}
 
 
static void set_clk_sleep_mode(void)
{
  __HAL_RCC_XSPI1_CLK_SLEEP_ENABLE();
  __HAL_RCC_XSPI2_CLK_SLEEP_ENABLE();
  __HAL_RCC_NPU_CLK_SLEEP_ENABLE();
  __HAL_RCC_CACHEAXI_CLK_SLEEP_ENABLE();
  __HAL_RCC_LTDC_CLK_SLEEP_ENABLE();
  __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE();
  __HAL_RCC_DCMIPP_CLK_SLEEP_ENABLE();
  __HAL_RCC_CSI_CLK_SLEEP_ENABLE();
  __HAL_RCC_FLEXRAM_MEM_CLK_SLEEP_ENABLE();
  __HAL_RCC_AXISRAM1_MEM_CLK_SLEEP_ENABLE();
  __HAL_RCC_AXISRAM2_MEM_CLK_SLEEP_ENABLE();
  __HAL_RCC_AXISRAM3_MEM_CLK_SLEEP_ENABLE();
  __HAL_RCC_AXISRAM4_MEM_CLK_SLEEP_ENABLE();
  __HAL_RCC_AXISRAM5_MEM_CLK_SLEEP_ENABLE();
  __HAL_RCC_AXISRAM6_MEM_CLK_SLEEP_ENABLE();
}
 
 
static void NPUCache_config(void)
{
  npu_cache_init();
  npu_cache_enable();
}
 
 
static void Security_Config(void)
{
  __HAL_RCC_RIFSC_CLK_ENABLE();
  RIMC_MasterConfig_t RIMC_master = {0};
  RIMC_master.MasterCID = RIF_CID_1;
  RIMC_master.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV;
  HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_NPU, &RIMC_master);
  HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_DMA2D, &RIMC_master);
  HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_DCMIPP, &RIMC_master);
  HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_LTDC1, &RIMC_master);
  HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_LTDC2, &RIMC_master);
  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_NPU,    RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_DMA2D,  RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_CSI,    RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_DCMIPP, RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_LTDC,   RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_LTDCL1, RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_LTDCL2, RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
}
 
 
static void IAC_Config(void)
{
  __HAL_RCC_IAC_CLK_ENABLE();
  __HAL_RCC_IAC_FORCE_RESET();
  __HAL_RCC_IAC_RELEASE_RESET();
}
 
 
void IAC_IRQHandler(void)
{
  while (1) {}
}
 
 
/* ============================================================================
 * DISPLAY HELPER FUNCTIONS
 * ============================================================================ */
 
static int clamp_point(int *x, int *y)
{
  int xi = *x, yi = *y;
  if (*x < (int)lcd_bg_area.X0)             *x = lcd_bg_area.X0;
  if (*y < (int)lcd_bg_area.Y0)             *y = lcd_bg_area.Y0;
  if (*x >= lcd_bg_area.X0 + lcd_bg_area.XSize) *x = lcd_bg_area.X0 + lcd_bg_area.XSize - 1;
  if (*y >= lcd_bg_area.Y0 + lcd_bg_area.YSize) *y = lcd_bg_area.Y0 + lcd_bg_area.YSize - 1;
  return (xi != *x) || (yi != *y);
}
 
 
static void convert_length(float32_t wi, float32_t hi, int *wo, int *ho)
{
  *wo = lcd_bg_area.XSize * wi;
  *ho = lcd_bg_area.YSize * hi;
}
 
 
static void convert_point(float32_t xi, float32_t yi, int *xo, int *yo)
{
  *xo = lcd_bg_area.XSize * xi + lcd_bg_area.X0;
  *yo = lcd_bg_area.YSize * yi + lcd_bg_area.Y0;
}
 
 
static void Display_binding_line(int x0, int y0, int x1, int y1, uint32_t color)
{
  clamp_point(&x0, &y0);
  clamp_point(&x1, &y1);
  UTIL_LCD_DrawLine(x0, y0, x1, y1, color);
}
 
 
static void Display_NetworkOutput(void *p_postprocess, uint32_t inference_ms)
{
#if POSTPROCESS_TYPE == POSTPROCESS_MPE_YOLO_V8_UF
  mpe_pp_outBuffer_t *rois = ((mpe_pp_out_t *) p_postprocess)->pOutBuff;
  uint32_t nb_rois = ((mpe_pp_out_t *) p_postprocess)->nb_detect;
#elif POSTPROCESS_TYPE == POSTPROCESS_SPE_MOVENET_UF
  spe_pp_outBuffer_t *roi = ((spe_pp_out_t *) p_postprocess)->pOutBuff;
#endif
  int ret;
 
  ret = HAL_LTDC_SetAddress_NoReload(&hlcd_ltdc,
        (uint32_t) lcd_fg_buffer[lcd_fg_buffer_rd_idx], LTDC_LAYER_2);
  assert(ret == HAL_OK);
 
  UTIL_LCD_FillRect(lcd_fg_area.X0, lcd_fg_area.Y0,
                    lcd_fg_area.XSize, lcd_fg_area.YSize, 0x00000000);
 
#if POSTPROCESS_TYPE == POSTPROCESS_MPE_YOLO_V8_UF
  for (int i = 0; i < nb_rois; i++)
    Display_mpe_Detection(&rois[i]);
  UTIL_LCDEx_PrintfAt(0, LINE(2), CENTER_MODE, "Objects %u", nb_rois);
#elif POSTPROCESS_TYPE == POSTPROCESS_SPE_MOVENET_UF
  Display_spe_Detection(roi);
#endif
 
  UTIL_LCD_SetBackColor(0x40000000);   /* Semi-transparent background */
  UTIL_LCDEx_PrintfAt(0, LINE(20), CENTER_MODE, "Inference: %ums", inference_ms);
  UTIL_LCD_SetBackColor(0);
 
  Display_WelcomeScreen();
 
  SCB_CleanDCache_by_Addr(lcd_fg_buffer[lcd_fg_buffer_rd_idx],
                           LCD_FG_FRAMEBUFFER_SIZE);
 
  ret = HAL_LTDC_ReloadLayer(&hlcd_ltdc, LTDC_RELOAD_VERTICAL_BLANKING, LTDC_LAYER_2);
  assert(ret == HAL_OK);
 
  lcd_fg_buffer_rd_idx = 1 - lcd_fg_buffer_rd_idx;
}
 
 
static void LCD_init(void)
{
  BSP_LCD_Init(0, LCD_ORIENTATION_LANDSCAPE);
 
  LayerConfig.X0          = lcd_bg_area.X0;
  LayerConfig.Y0          = lcd_bg_area.Y0;
  LayerConfig.X1          = lcd_bg_area.X0 + lcd_bg_area.XSize;
  LayerConfig.Y1          = lcd_bg_area.Y0 + lcd_bg_area.YSize;
  LayerConfig.PixelFormat = LCD_PIXEL_FORMAT_RGB565;
  LayerConfig.Address     = (uint32_t) lcd_bg_buffer;
  BSP_LCD_ConfigLayer(0, LTDC_LAYER_1, &LayerConfig);
 
  LayerConfig.X0          = lcd_fg_area.X0;
  LayerConfig.Y0          = lcd_fg_area.Y0;
  LayerConfig.X1          = lcd_fg_area.X0 + lcd_fg_area.XSize;
  LayerConfig.Y1          = lcd_fg_area.Y0 + lcd_fg_area.YSize;
  LayerConfig.PixelFormat = LCD_PIXEL_FORMAT_ARGB4444;
  LayerConfig.Address     = (uint32_t) lcd_fg_buffer;
  BSP_LCD_ConfigLayer(0, LTDC_LAYER_2, &LayerConfig);
 
  UTIL_LCD_SetFuncDriver(&LCD_Driver);
  UTIL_LCD_SetLayer(LTDC_LAYER_2);
  UTIL_LCD_Clear(0x00000000);
  UTIL_LCD_SetFont(&Font20);
  UTIL_LCD_SetTextColor(UTIL_LCD_COLOR_WHITE);
 
#if POSTPROCESS_TYPE == POSTPROCESS_MPE_YOLO_V8_UF
  Display_mpe_InitFunctions(clamp_point, convert_length, convert_point,
                             Display_binding_line);
#elif POSTPROCESS_TYPE == POSTPROCESS_SPE_MOVENET_UF
  Display_spe_InitFunctions(clamp_point, convert_length, convert_point,
                             Display_binding_line);
#endif
}
 
 
static void Display_WelcomeScreen(void)
{
  static uint32_t t0 = 0;
  if (t0 == 0) t0 = HAL_GetTick();
 
  if (HAL_GetTick() - t0 < 4000)
  {
    UTIL_LCD_FillRGBRect(300, 100, (uint8_t *) stlogo, 200, 107);
    UTIL_LCD_SetBackColor(0x40000000);
    UTIL_LCDEx_PrintfAt(0, LINE(16), CENTER_MODE, "Pose estimation");
    UTIL_LCDEx_PrintfAt(0, LINE(17), CENTER_MODE, WELCOME_MSG_1);
    UTIL_LCDEx_PrintfAt(0, LINE(18), CENTER_MODE, WELCOME_MSG_2);
    UTIL_LCD_SetBackColor(0);
  }
}
 
 
HAL_StatusTypeDef MX_DCMIPP_ClockConfig(DCMIPP_HandleTypeDef *hdcmipp)
{
  RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0};
  HAL_StatusTypeDef ret = HAL_OK;
 
  RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_DCMIPP;
  RCC_PeriphCLKInitStruct.DcmippClockSelection = RCC_DCMIPPCLKSOURCE_IC17;
  RCC_PeriphCLKInitStruct.ICSelection[RCC_IC17].ClockSelection = RCC_ICCLKSOURCE_PLL2;
  RCC_PeriphCLKInitStruct.ICSelection[RCC_IC17].ClockDivider = 3;
  ret = HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
  if (ret) return ret;
 
  RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CSI;
  RCC_PeriphCLKInitStruct.ICSelection[RCC_IC18].ClockSelection = RCC_ICCLKSOURCE_PLL1;
  RCC_PeriphCLKInitStruct.ICSelection[RCC_IC18].ClockDivider = 40;
  ret = HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
  return ret;
}
 
 
static void SystemClock_Config(void)
{
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0};
 
  BSP_SMPS_Init(SMPS_VOLTAGE_OVERDRIVE);  /* Set VDDCORE=0.9V for 800MHz+ operation */
 
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_NONE;
 
  RCC_OscInitStruct.PLL1.PLLState  = RCC_PLL_ON;
  RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSI;
  RCC_OscInitStruct.PLL1.PLLM = 2; RCC_OscInitStruct.PLL1.PLLN = 25;
  RCC_OscInitStruct.PLL1.PLLFractional = 0;
  RCC_OscInitStruct.PLL1.PLLP1 = 1; RCC_OscInitStruct.PLL1.PLLP2 = 1;
 
  RCC_OscInitStruct.PLL2.PLLState  = RCC_PLL_ON;
  RCC_OscInitStruct.PLL2.PLLSource = RCC_PLLSOURCE_HSI;
  RCC_OscInitStruct.PLL2.PLLM = 8; RCC_OscInitStruct.PLL2.PLLN = 125;
  RCC_OscInitStruct.PLL2.PLLFractional = 0;
  RCC_OscInitStruct.PLL2.PLLP1 = 1; RCC_OscInitStruct.PLL2.PLLP2 = 1;
 
  RCC_OscInitStruct.PLL3.PLLState  = RCC_PLL_ON;
  RCC_OscInitStruct.PLL3.PLLSource = RCC_PLLSOURCE_HSI;
  RCC_OscInitStruct.PLL3.PLLM = 8; RCC_OscInitStruct.PLL3.PLLN = 225;
  RCC_OscInitStruct.PLL3.PLLFractional = 0;
  RCC_OscInitStruct.PLL3.PLLP1 = 1; RCC_OscInitStruct.PLL3.PLLP2 = 2;
 
  RCC_OscInitStruct.PLL4.PLLState  = RCC_PLL_ON;
  RCC_OscInitStruct.PLL4.PLLSource = RCC_PLLSOURCE_HSI;
  RCC_OscInitStruct.PLL4.PLLM = 8; RCC_OscInitStruct.PLL4.PLLN = 225;
  RCC_OscInitStruct.PLL4.PLLFractional = 0;
  RCC_OscInitStruct.PLL4.PLLP1 = 6; RCC_OscInitStruct.PLL4.PLLP2 = 6;
 
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) while(1);
 
  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK |
                                  RCC_CLOCKTYPE_HCLK   | RCC_CLOCKTYPE_PCLK1  |
                                  RCC_CLOCKTYPE_PCLK2  | RCC_CLOCKTYPE_PCLK4  |
                                  RCC_CLOCKTYPE_PCLK5);
 
  RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_IC1;        /* CPU: PLL1/1 = 800 MHz */
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_IC2_IC6_IC11;
  RCC_ClkInitStruct.IC1Selection.ClockSelection  = RCC_ICCLKSOURCE_PLL1; RCC_ClkInitStruct.IC1Selection.ClockDivider  = 1;
  RCC_ClkInitStruct.IC2Selection.ClockSelection  = RCC_ICCLKSOURCE_PLL1; RCC_ClkInitStruct.IC2Selection.ClockDivider  = 2;  /* AXI: 400 MHz */
  RCC_ClkInitStruct.IC6Selection.ClockSelection  = RCC_ICCLKSOURCE_PLL2; RCC_ClkInitStruct.IC6Selection.ClockDivider  = 1;  /* NPU: 1000 MHz */
  RCC_ClkInitStruct.IC11Selection.ClockSelection = RCC_ICCLKSOURCE_PLL3; RCC_ClkInitStruct.IC11Selection.ClockDivider = 1;  /* AXISRAM: 900 MHz */
  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;   /* HCLK: 200 MHz */
  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
  RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV1;
 
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) while(1);
 
  RCC_PeriphCLKInitStruct.PeriphClockSelection  = RCC_PERIPHCLK_XSPI1 | RCC_PERIPHCLK_XSPI2;
  RCC_PeriphCLKInitStruct.Xspi1ClockSelection   = RCC_XSPI1CLKSOURCE_HCLK;  /* 200 MHz */
  RCC_PeriphCLKInitStruct.Xspi2ClockSelection   = RCC_XSPI2CLKSOURCE_HCLK;  /* 200 MHz */
  if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct) != HAL_OK) while(1);
}